#if defined(TSINGMA_MX)
#include "sal.h"
#include "usw/include/drv_enum.h"

#include "ctc_error.h"

#include "sys_usw_common.h"
#include "sys_usw_interrupt.h"
#include "../sys_usw_interrupt_priv.h"

enum sys_tmm_interrupt_type_e
{
    SYS_TMM_INTR_CHIP_FATAL = 0,
    SYS_TMM_INTR_CHIP_NORMAL = 1,
    SYS_TMM_INTR_FUNC_PTP_TS_CAPTURE_FIFO = 2,
    SYS_TMM_INTR_FUNC_PTP_TOD_PULSE_IN = 3,
    SYS_TMM_INTR_FUNC_PTP_TOD_CODE_IN_RDY = 4,
    SYS_TMM_INTR_FUNC_PTP_SYNC_PULSE_IN = 5,
    SYS_TMM_INTR_FUNC_PTP_SYNC_CODE_IN_RDY = 6,
    SYS_TMM_INTR_FUNC_PTP_SYNC_CODE_IN_ACC = 7,
    SYS_TMM_INTR_FUNC_TCAM_SCAN_ERROR = 8,
    SYS_TMM_INTR_FUNC_SVC_POLICING_STATUS_ADDR = 9,
    SYS_TMM_INTR_FUNC_STMCTL_STATE = 10,
    SYS_TMM_INTR_FUNC_IPFIX_USEAGE_OVERFLOW = 11,
	SYS_TMM_INTR_FUNC_FIB_ACC_LEARN_OUT_FIFO = 12,
    SYS_TMM_INTR_FUNC_STATS_STATUS_ADDR = 13,
    SYS_TMM_INTR_FUNC_MET_LINK_SCAN_DONE = 14,
    SYS_TMM_INTR_FUNC_OAM_AUTO_GEN = 15,
    SYS_TMM_INTR_FUNC_OAM_DEFECT_CACHE = 16,
    SYS_TMM_INTR_FUNC_DP1_MDIO_XG_CHANGE_0 = 17,
    SYS_TMM_INTR_FUNC_DP1_MDIO_XG_CHANGE_1 = 18,
    SYS_TMM_INTR_FUNC_MDIO_XG_CHANGE_0 = 19,
    SYS_TMM_INTR_FUNC_MDIO_XG_CHANGE_1 = 20,
    SYS_TMM_INTR_FUNC_SPN_DMA_DROPL = 21,
    SYS_TMM_INTR_FUNC_SPN_DMA_DROPM = 22,
    SYS_TMM_INTR_FUNC_SPN_CPU_REPORTL = 23,
    SYS_TMM_INTR_FUNC_SPN_CPU_REPORTM = 24,
    SYS_TMM_INTR_FUNC_CPU_MAC = 25,
    SYS_TMM_INTR_FUNC_BSR_C2C_PKT_CONGESTION = 26,
    SYS_TMM_INTR_FUNC_BSR_CRITICAL_PKT_CONGESTION = 27,
    SYS_TMM_INTR_FUNC_BSR_DMA_CONGESTION = 28,
    SYS_TMM_INTR_FUNC_BSR_OAM_CONGESTION = 29,
    SYS_TMM_INTR_FUNC_BSR_TOTAL_CONGESTION = 30,
    SYS_TMM_INTR_FUNC_DP1_BSR_C2C_PKT_CONGESTION = 31,
    SYS_TMM_INTR_FUNC_DP1_BSR_CRITICAL_PKT_CONGESTION = 32,
    SYS_TMM_INTR_FUNC_DP1_BSR_DMA_CONGESTION = 33,
    SYS_TMM_INTR_FUNC_DP1_BSR_OAM_CONGESTION = 34,
    SYS_TMM_INTR_FUNC_DP1_BSR_TOTAL_CONGESTION = 35,
    SYS_TMM_INTR_FUNC_DP1_FLEX_DP0 = 36,
    SYS_TMM_INTR_FUNC_DP1_FLEX_DP1 = 37,
    SYS_TMM_INTR_FUNC_DP1_OMC_TR = 38,
    SYS_TMM_INTR_FUNC_DP1_OMC_TL = 39,
    SYS_TMM_INTR_FUNC_DP1_OMC_BR = 40,
    SYS_TMM_INTR_FUNC_DP1_OMC_BL = 41,
    SYS_TMM_INTR_FUNC_DP0_MACSEC_RX = 42,
    SYS_TMM_INTR_FUNC_DP1_MACSEC_RX = 43,
    SYS_TMM_INTR_FUNC_DP0_MACSEC_TX = 44,
    SYS_TMM_INTR_FUNC_DP1_MACSEC_TX = 45,
    SYS_TMM_INTR_FUNC_DP0_MC_MAC0 = 46,
    SYS_TMM_INTR_FUNC_DP0_MC_MAC1 = 47,
    SYS_TMM_INTR_FUNC_DP0_MC_MAC2 = 48,
    SYS_TMM_INTR_FUNC_DP0_MC_MAC3 = 49,
    SYS_TMM_INTR_FUNC_DP1_MC_MAC0 = 50,
    SYS_TMM_INTR_FUNC_DP1_MC_MAC1 = 51,
    SYS_TMM_INTR_FUNC_DP1_MC_MAC2 = 52,
    SYS_TMM_INTR_FUNC_DP1_MC_MAC3 = 53,
    SYS_TMM_INTR_FUNC_PTP_TOD_PULSE = 54,
    SYS_TMM_INTR_FUNC_PTP_SYNC_PULSE = 55,
    SYS_TMM_INTR_FUNC_FLEXE0_MCU_REQ = 56,
    SYS_TMM_INTR_FUNC_FLEXE1_MCU_REQ = 57,
    SYS_TMM_INTR_FUNC_MISC_MCU_REQ = 58,
    SYS_TMM_INTR_FUNC_PCIE_BURST_DONE = 59,
    SYS_TMM_INTR_FUNC_DMA = 60,
    SYS_TMM_INTR_FUNC_ECPU = 61,
    SYS_TMM_INTR_FUNC_SCPU = 62,

    SYS_TMM_INTR_MAX = 63
};
typedef enum sys_tmm_interrupt_type_e sys_tmm_interrupt_type_t;
/*Generate the sub low table list*/

#define DEF_D(RegName, bit) \
    }; \
  uint32 RegName##_sub_low_list_tmm_##bit[] = {

#define DEF_F(RegName, bit, InstNum) \
    RegName##_t | InstNum << 24,

#define DEF_F_NULL(bit) \
    0,

#define DEF_DD(RegName, bit) \
    }; \
    uint32 RegName##_sub_low_list_tmm_##bit[] = {

#define DEF_FF_NULL(RegName, bit) \
    0,

#define DEF_FF(RegName, bit, InstNum) \
    RegName##_t | InstNum << 24,


uint32 sub_low_1st_tmm[] = {0,
#include "sys_tmm_interrupt.h"
};

#undef DEF_D
#undef DEF_F
#undef DEF_F_NULL
#undef DEF_DD
#undef DEF_FF_NULL
#undef DEF_FF


/*Generate the sub low table list*/
#define DEF_D(RegName, bit)
#define DEF_F(RegName, bit, InstNum)
#define DEF_F_NULL(bit)

#define DEF_DD(RegName, bit) \
    }; \
  sys_intr_tbl_array_t RegName##_sub_list_tmm[] = {

#define DEF_FF_NULL(RegName, bit) \
    {NULL, 0},

#define DEF_FF(RegName, bit, InstNum) \
    {RegName##_sub_low_list_tmm_##bit, sizeof(RegName##_sub_low_list_tmm_##bit)/sizeof(RegName##_sub_low_list_tmm_##bit[0])},

sys_intr_tbl_array_t sub_1st_tmm[] = {{0, 0},
#include "sys_tmm_interrupt.h"
};

#define SUB_TABLE_LIST(RegName)  RegName##_sub_list_tmm

extern int32 sys_usw_qos_fcdl_state_isr(uint8 lchip, uint16 mac_id);
extern int32 _sys_usw_intr_log_normal_intr(uint8 lchip, sys_intr_abnormal_log_t log_intr);
extern int32 _sys_usw_interrupt_release_fatal(uint8 lchip, sys_intr_type_t* p_type, uint32 enable);
extern int32 _sys_usw_interrupt_release_normal(uint8 lchip, sys_intr_type_t* p_type, uint32 enable);

int32 sys_tmm_interrupt_db_init(uint8 lchip)
{
    uint8 intr_idx = 0;
    sys_intr_func_intr_info_t* p_func_intr_tmm = NULL;

    p_usw_intr_master[lchip]->p_intr_low_fatal = SUB_TABLE_LIST(SupIntrFatal);
    p_usw_intr_master[lchip]->p_intr_low_normal = SUB_TABLE_LIST(SupIntrNormal);
    p_usw_intr_master[lchip]->p_intr_sub_abnormal = SUB_TABLE_LIST(SupIntrGenCtl);

    p_usw_intr_master[lchip]->fatal_sub_cnt = sizeof(SUB_TABLE_LIST(SupIntrFatal)) / sizeof(sys_intr_tbl_array_t);
    p_usw_intr_master[lchip]->normal_sub_cnt =  sizeof(SUB_TABLE_LIST(SupIntrNormal)) / sizeof(sys_intr_tbl_array_t);
    p_usw_intr_master[lchip]->intr_word_num = 2;

    p_usw_intr_master[lchip]->p_intr_func = mem_malloc(MEM_SYSTEM_MODULE, sizeof(sys_intr_func_intr_info_t)*SYS_TMM_INTR_MAX);
    if (!p_usw_intr_master[lchip]->p_intr_func)
    {
        return CTC_E_NO_MEMORY;
    }
    sal_memset(p_usw_intr_master[lchip]->p_intr_func, 0, sizeof(sys_intr_func_intr_info_t)*SYS_TMM_INTR_MAX);

    for (intr_idx = SYS_TMM_INTR_FUNC_PTP_TS_CAPTURE_FIFO; intr_idx < SYS_TMM_INTR_MAX; intr_idx++)
    {
        p_func_intr_tmm = &p_usw_intr_master[lchip]->p_intr_func[intr_idx];
        p_func_intr_tmm->tbl_size = 2;
        switch (intr_idx)
        {
            case SYS_TMM_INTR_FUNC_PTP_TS_CAPTURE_FIFO:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 0;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_PTP_TS_CAPTURE_FIFO;
                break;
            case SYS_TMM_INTR_FUNC_PTP_TOD_PULSE_IN:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 1;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_PTP_TOD_PULSE_IN;
                break;
            case SYS_TMM_INTR_FUNC_PTP_TOD_CODE_IN_RDY:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 2;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_PTP_TOD_CODE_IN_RDY;
                break;
            case SYS_TMM_INTR_FUNC_PTP_SYNC_PULSE_IN:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 3;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_PTP_SYNC_PULSE_IN;
                break;
            case SYS_TMM_INTR_FUNC_PTP_SYNC_CODE_IN_RDY:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 4;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_PTP_SYNC_CODE_IN_RDY;
                break;
            case SYS_TMM_INTR_FUNC_PTP_SYNC_CODE_IN_ACC:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 5;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_PTP_SYNC_CODE_IN_RDY;
                break;
            case SYS_TMM_INTR_FUNC_TCAM_SCAN_ERROR:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 6;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_TCAM_SCAN_ERROR;
                break;
             case SYS_TMM_INTR_FUNC_SVC_POLICING_STATUS_ADDR:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 7;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR;
                break;
            case SYS_TMM_INTR_FUNC_STMCTL_STATE:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 8;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_STMCTL_STATE;
                break;
            case SYS_TMM_INTR_FUNC_IPFIX_USEAGE_OVERFLOW:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 9;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_IPFIX_USEAGE_OVERFLOW;
                break;
            case SYS_TMM_INTR_FUNC_FIB_ACC_LEARN_OUT_FIFO:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 10;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_FIB_ACC_LEARN_OUT_FIFO;
                break;
            case SYS_TMM_INTR_FUNC_STATS_STATUS_ADDR:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 11;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_STATS_STATUS_ADDR;
                break;
            case SYS_TMM_INTR_FUNC_MET_LINK_SCAN_DONE:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 12;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_MET_LINK_SCAN_DONE;
                break;
            case SYS_TMM_INTR_FUNC_OAM_AUTO_GEN:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 13;
                p_func_intr_tmm->sub_tbl_id = OamAutoGenPktInterruptFunc_t;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_OAM_AUTO_GEN;               
                p_func_intr_tmm->tbl_size = 3;
                break;
            case SYS_TMM_INTR_FUNC_OAM_DEFECT_CACHE:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 14;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_OAM_DEFECT_CACHE;
                break;
            case SYS_TMM_INTR_FUNC_DP1_MDIO_XG_CHANGE_0:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 15;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_MDIO_XG_CHANGE_0;
                break;
            case SYS_TMM_INTR_FUNC_DP1_MDIO_XG_CHANGE_1:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 16;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_MDIO_XG_CHANGE_1;
                break;
            case SYS_TMM_INTR_FUNC_MDIO_XG_CHANGE_0:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 17;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_MDIO_XG_CHANGE_0;
                break;
            case SYS_TMM_INTR_FUNC_MDIO_XG_CHANGE_1:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 18;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_MDIO_XG_CHANGE_1;
                break;
            case SYS_TMM_INTR_FUNC_SPN_DMA_DROPL:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 19;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_SPN_DMA_DROPL;
                break;
            case SYS_TMM_INTR_FUNC_SPN_DMA_DROPM:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 20;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_SPN_DMA_DROPM;
                break;
            case SYS_TMM_INTR_FUNC_SPN_CPU_REPORTL:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 21;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_SPN_CPU_REPORTL;
                break;
            case SYS_TMM_INTR_FUNC_SPN_CPU_REPORTM:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 22;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_SPN_CPU_REPORTM;
                break;
            case SYS_TMM_INTR_FUNC_CPU_MAC:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 23;
                p_func_intr_tmm->sub_tbl_id = CpuMacProcInterruptFunc_t;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_CPU_MAC;
                p_func_intr_tmm->tbl_size = 1;
                break;
            case SYS_TMM_INTR_FUNC_BSR_C2C_PKT_CONGESTION:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 24;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_BSR_C2C_PKT_CONGESTION;
                break;
            case SYS_TMM_INTR_FUNC_BSR_CRITICAL_PKT_CONGESTION:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 25;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_BSR_CRITICAL_PKT_CONGESTION;
                break;
            case SYS_TMM_INTR_FUNC_BSR_DMA_CONGESTION:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 26;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_BSR_DMA_CONGESTION;
                break;
            case SYS_TMM_INTR_FUNC_BSR_OAM_CONGESTION:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 27;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_BSR_OAM_CONGESTION;
                break;
            case SYS_TMM_INTR_FUNC_BSR_TOTAL_CONGESTION:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 28;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_BSR_TOTAL_CONGESTION;
                break;
            case SYS_TMM_INTR_FUNC_DP1_BSR_C2C_PKT_CONGESTION:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 29;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_BSR_C2C_PKT_CONGESTION;
                break;
            case SYS_TMM_INTR_FUNC_DP1_BSR_CRITICAL_PKT_CONGESTION:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 30;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_BSR_CRITICAL_PKT_CONGESTION;
                break;
            case SYS_TMM_INTR_FUNC_DP1_BSR_DMA_CONGESTION:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 31;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_BSR_DMA_CONGESTION;
                break;
            case SYS_TMM_INTR_FUNC_DP1_BSR_OAM_CONGESTION:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 32;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_BSR_OAM_CONGESTION;
                break;
            case SYS_TMM_INTR_FUNC_DP1_BSR_TOTAL_CONGESTION:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 33;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_BSR_TOTAL_CONGESTION;
                break;
            case SYS_TMM_INTR_FUNC_DP1_FLEX_DP0:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 34;
                p_func_intr_tmm->sub_tbl_id = FlexeMgrInterruptFunc_t | (0<<24);
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_FLEX_DP0;
                p_func_intr_tmm->tbl_size = 5;
                break;
            case SYS_TMM_INTR_FUNC_DP1_FLEX_DP1:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 35;
                p_func_intr_tmm->sub_tbl_id = FlexeMgrInterruptFunc_t | (1<<24);
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_FLEX_DP1;                
                p_func_intr_tmm->tbl_size = 5;
                break;
            case SYS_TMM_INTR_FUNC_DP1_OMC_TR:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 36;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_OMC_TR;
                break;
            case SYS_TMM_INTR_FUNC_DP1_OMC_TL:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 37;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_OMC_TL;
                break;
            case SYS_TMM_INTR_FUNC_DP1_OMC_BR:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 38;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_OMC_BR;
                break;
            case SYS_TMM_INTR_FUNC_DP1_OMC_BL:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 39;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_OMC_BL;
                break;
            case SYS_TMM_INTR_FUNC_DP0_MACSEC_RX:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 40;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP0_MACSEC_RX;
                break;
            case SYS_TMM_INTR_FUNC_DP1_MACSEC_RX:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 41;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_MACSEC_RX;
                break;
            case SYS_TMM_INTR_FUNC_DP0_MACSEC_TX:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 42;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP0_MACSEC_TX;
                break;
            case SYS_TMM_INTR_FUNC_DP1_MACSEC_TX:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 43;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_MACSEC_TX;
                break;
            case SYS_TMM_INTR_FUNC_DP0_MC_MAC0:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 44;
                p_func_intr_tmm->sub_tbl_id = CtcHsCtlInterruptFunc_t | (0<<24);
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP0_MC_MAC0;                
                p_func_intr_tmm->tbl_size = 5;
                break;
            case SYS_TMM_INTR_FUNC_DP0_MC_MAC1:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 45;
                p_func_intr_tmm->sub_tbl_id = CtcHsCtlInterruptFunc_t | (1<<24);
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP0_MC_MAC1;                
                p_func_intr_tmm->tbl_size = 5;
                break;
            case SYS_TMM_INTR_FUNC_DP0_MC_MAC2:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 46;
                p_func_intr_tmm->sub_tbl_id = CtcCsCtlInterruptFunc_t | (0<<24);
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP0_MC_MAC2;                
                p_func_intr_tmm->tbl_size = 5;
                break;
            case SYS_TMM_INTR_FUNC_DP0_MC_MAC3:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 47;
                p_func_intr_tmm->sub_tbl_id = CtcCsCtlInterruptFunc_t | (1<<24);
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP0_MC_MAC3;                
                p_func_intr_tmm->tbl_size = 5;
                break;
            case SYS_TMM_INTR_FUNC_DP1_MC_MAC0:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 48;
                p_func_intr_tmm->sub_tbl_id = CtcHsCtlInterruptFunc_t | (2<<24);
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_MC_MAC0;                
                p_func_intr_tmm->tbl_size = 5;
                break;
            case SYS_TMM_INTR_FUNC_DP1_MC_MAC1:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 49;
                p_func_intr_tmm->sub_tbl_id = CtcHsCtlInterruptFunc_t | (3<<24);
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_MC_MAC1;                
                p_func_intr_tmm->tbl_size = 5;
                break;
            case SYS_TMM_INTR_FUNC_DP1_MC_MAC2:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 50;
                p_func_intr_tmm->sub_tbl_id = CtcCsCtlInterruptFunc_t | (2<<24);
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_MC_MAC2;                
                p_func_intr_tmm->tbl_size = 5;
                break;
            case SYS_TMM_INTR_FUNC_DP1_MC_MAC3:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 51;
                p_func_intr_tmm->sub_tbl_id = CtcCsCtlInterruptFunc_t | (3<<24);
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_DP1_MC_MAC3;                
                p_func_intr_tmm->tbl_size = 5;
                break;
            case SYS_TMM_INTR_FUNC_PTP_TOD_PULSE:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 52;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_PTP_TOD_PULSE;
                break;
            case SYS_TMM_INTR_FUNC_PTP_SYNC_PULSE:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 53;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_PTP_SYNC_PULSE;
                break;
            case SYS_TMM_INTR_FUNC_FLEXE0_MCU_REQ:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 54;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_FLEXE0_MCU_REQ;
                break;
            case SYS_TMM_INTR_FUNC_FLEXE1_MCU_REQ:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 55;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_FLEXE1_MCU_REQ;
                break;
            case SYS_TMM_INTR_FUNC_MISC_MCU_REQ:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 56;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_MISC_MCU_REQ;
                break;
            case SYS_TMM_INTR_FUNC_PCIE_BURST_DONE:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 57;
                p_func_intr_tmm->sub_tbl_id = PcieIntfInterruptFunc_t;
                p_func_intr_tmm->common_type = SYS_INTR_PCIE_BURST_DONE;                
                p_func_intr_tmm->tbl_size = 1;
                break;
            case SYS_TMM_INTR_FUNC_DMA:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 58;
                p_func_intr_tmm->sub_tbl_id = DRV_FROM_AT(lchip)? DmaCtlIntrFunc0_t : DmaCtlIntrFunc_t;
                p_func_intr_tmm->common_type = SYS_INTR_DMA;                
                p_func_intr_tmm->tbl_size = 1;
                break;
            case SYS_TMM_INTR_FUNC_ECPU:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 59;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_ECPU;
                break;
            case SYS_TMM_INTR_FUNC_SCPU:
                p_func_intr_tmm->tbl_id = SupIntrFunc_t;
                p_func_intr_tmm->bit_offset = 60;
                p_func_intr_tmm->common_type = SYS_INTR_FUNC_SCPU;
                break;
        }
    }

    return 0;
}

/* This function is to get intr type at specific position in intrvec table(SupCtlIntrVec) */

/* This function is to get the corresponding position of specific intr type in intrvec table(SupCtlIntrVec) */
int32 sys_tmm_interrupt_get_intrvec_offset(uint8 lchip, uint32 intr_type, uint32 *p_offset)
{
    CTC_PTR_VALID_CHECK(p_offset);

    switch (intr_type)
    {
        case SYS_INTR_CHIP_FATAL:
            *p_offset = 0;
            break;
        case SYS_INTR_CHIP_NORMAL:
            *p_offset = 1;
            break;
        case SYS_INTR_FUNC_PTP_TS_CAPTURE_FIFO:
            *p_offset = 2;
            break;
        case SYS_INTR_FUNC_PTP_TOD_PULSE_IN:
            *p_offset = 3;
            break;
        case SYS_INTR_FUNC_PTP_TOD_CODE_IN_RDY:
            *p_offset = 4;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_PULSE_IN:
            *p_offset = 5;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_CODE_IN_RDY:
            *p_offset = 6;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_CODE_IN_ACC:
            *p_offset = 7;
            break;
        case SYS_INTR_FUNC_TCAM_SCAN_ERROR:
            *p_offset = 8;
            break;
        case SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR:
            *p_offset = 9;
            break;
        case SYS_INTR_FUNC_STMCTL_STATE:
            *p_offset = 10;
            break;
        case SYS_INTR_FUNC_IPFIX_USEAGE_OVERFLOW:
            *p_offset = 11;
            break;
        case SYS_INTR_FUNC_FIB_ACC_LEARN_OUT_FIFO:
            *p_offset = 12;
            break;
        case SYS_INTR_FUNC_STATS_STATUS_ADDR:
            *p_offset = 13;
            break;
        case SYS_INTR_FUNC_MET_LINK_SCAN_DONE:
            *p_offset = 14;
            break;
        case SYS_INTR_FUNC_OAM_AUTO_GEN:
            *p_offset = 15;
            break;
        case SYS_INTR_FUNC_OAM_DEFECT_CACHE:
            *p_offset = 16;
            break;
        case SYS_INTR_FUNC_DP1_MDIO_XG_CHANGE_0:
            *p_offset = 17;
            break;
        case SYS_INTR_FUNC_DP1_MDIO_XG_CHANGE_1:
            *p_offset = 18;
            break;
        case SYS_INTR_FUNC_MDIO_XG_CHANGE_0:
            *p_offset = 19;
            break;
        case SYS_INTR_FUNC_MDIO_XG_CHANGE_1:
            *p_offset = 20;
            break;
        case SYS_INTR_FUNC_SPN_DMA_DROPL:
            *p_offset = 21;
            break;
        case SYS_INTR_FUNC_SPN_DMA_DROPM:
            *p_offset = 22;
            break;
        case SYS_INTR_FUNC_SPN_CPU_REPORTL:
            *p_offset = 23;
            break;
        case SYS_INTR_FUNC_SPN_CPU_REPORTM:
            *p_offset = 24;
            break;
        case SYS_INTR_FUNC_CPU_MAC:
            *p_offset = 25;
            break;
        case SYS_INTR_FUNC_BSR_C2C_PKT_CONGESTION:
            *p_offset = 26;
            break;
        case SYS_INTR_FUNC_BSR_CRITICAL_PKT_CONGESTION:
            *p_offset = 27;
            break;
        case SYS_INTR_FUNC_BSR_DMA_CONGESTION:
            *p_offset = 28;
            break;
        case SYS_INTR_FUNC_BSR_OAM_CONGESTION:
            *p_offset = 29;
            break;
        case SYS_INTR_FUNC_BSR_TOTAL_CONGESTION:
            *p_offset = 30;
            break;
        case SYS_INTR_FUNC_DP1_BSR_C2C_PKT_CONGESTION:
            *p_offset = 31;
            break;
        case SYS_INTR_FUNC_DP1_BSR_CRITICAL_PKT_CONGESTION:
            *p_offset = 32;
            break;
        case SYS_INTR_FUNC_DP1_BSR_DMA_CONGESTION:
            *p_offset = 33;
            break;
        case SYS_INTR_FUNC_DP1_BSR_OAM_CONGESTION:
            *p_offset = 34;
            break;
        case SYS_INTR_FUNC_DP1_BSR_TOTAL_CONGESTION:
            *p_offset = 35;
            break;
        case SYS_INTR_FUNC_FLEX_DP0:
            *p_offset = 36;
            break;
        case SYS_INTR_FUNC_FLEX_DP1:
            *p_offset = 37;
            break;
        case SYS_INTR_FUNC_OMC_TR:
            *p_offset = 38;
            break;
        case SYS_INTR_FUNC_OMC_TL:
            *p_offset = 39;
            break;
        case SYS_INTR_FUNC_OMC_BR:
            *p_offset = 40;
            break;
        case SYS_INTR_FUNC_OMC_BL:
            *p_offset = 41;
            break;
        case SYS_INTR_FUNC_DP0_MACSEC_RX:
            *p_offset = 42;
            break;
        case SYS_INTR_FUNC_DP1_MACSEC_RX:
            *p_offset = 43;
            break;
        case SYS_INTR_FUNC_DP0_MACSEC_TX:
            *p_offset = 44;
            break;
        case SYS_INTR_FUNC_DP1_MACSEC_TX:
            *p_offset = 45;
            break;
        case SYS_INTR_FUNC_DP0_MC_MAC0:
            *p_offset = 46;
            break;
        case SYS_INTR_FUNC_DP0_MC_MAC1:
            *p_offset = 47;
            break;
        case SYS_INTR_FUNC_DP0_MC_MAC2:
            *p_offset = 48;
            break;
        case SYS_INTR_FUNC_DP0_MC_MAC3:
            *p_offset = 49;
            break;
        case SYS_INTR_FUNC_DP1_MC_MAC0:
            *p_offset = 50;
            break;
        case SYS_INTR_FUNC_DP1_MC_MAC1:
            *p_offset = 51;
            break;
        case SYS_INTR_FUNC_DP1_MC_MAC2:
            *p_offset = 52;
            break;
        case SYS_INTR_FUNC_DP1_MC_MAC3:
            *p_offset = 53;
            break;
	 case SYS_INTR_FUNC_PTP_TOD_PULSE:
            *p_offset = 54;
            break;
	 case SYS_INTR_FUNC_PTP_SYNC_PULSE:
            *p_offset = 55;
            break;
	 case SYS_INTR_FUNC_FLEXE0_MCU_REQ:
            *p_offset = 56;
            break;
	 case SYS_INTR_FUNC_FLEXE1_MCU_REQ:
            *p_offset = 57;
            break;
	 case SYS_INTR_FUNC_MISC_MCU_REQ:
            *p_offset = 58;
            break;
        case SYS_INTR_PCIE_BURST_DONE:
            *p_offset = 59;
            break;
        case SYS_INTR_DMA:
            *p_offset = 60;
            break;
        case SYS_INTR_FUNC_ECPU:
            *p_offset = 61;
            break;
        case SYS_INTR_FUNC_SCPU:
            *p_offset = 62;
            break;
        default:
            *p_offset = 0xFFFFFFFF; /* invalid value */
            return CTC_E_NOT_SUPPORT;
            break;
    }

    return CTC_E_NONE;
}


int32 sys_tmm_interrupt_get_sup_info(uint8 lchip, uint32 intr_type, uint32 *p_sup_table_id, uint16 *p_bit_offset, uint32 *p_func_table_id)
{
    CTC_PTR_VALID_CHECK(p_sup_table_id);
    CTC_PTR_VALID_CHECK(p_bit_offset);

    switch (intr_type)
    {
        case SYS_INTR_CHIP_FATAL:
            *p_sup_table_id = SupIntrFatal_t;
            *p_bit_offset = 0; /* no use */
            break;
        case SYS_INTR_CHIP_NORMAL:
            *p_sup_table_id = SupIntrNormal_t;
            *p_bit_offset = 0; /* no use */
            break;


        case SYS_INTR_FUNC_PTP_TS_CAPTURE_FIFO:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 0;
            break;
        case SYS_INTR_FUNC_PTP_TOD_PULSE_IN:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 1;
            break;
        case SYS_INTR_FUNC_PTP_TOD_CODE_IN_RDY:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 2;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_PULSE_IN:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 3;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_CODE_IN_RDY:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 4;
            break;


        case SYS_INTR_FUNC_PTP_SYNC_CODE_IN_ACC:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 5;
            break;
        case SYS_INTR_FUNC_TCAM_SCAN_ERROR:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 6;
            break;
        case SYS_INTR_FUNC_SVC_POLICING_STATUS_ADDR:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 7;
            break;
        case SYS_INTR_FUNC_STMCTL_STATE:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 8;
            break;
        case SYS_INTR_FUNC_IPFIX_USEAGE_OVERFLOW:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 9;
            break;
        case SYS_INTR_FUNC_FIB_ACC_LEARN_OUT_FIFO:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 10;
            break;
        case SYS_INTR_FUNC_STATS_STATUS_ADDR:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 11;
            break;
        case SYS_INTR_FUNC_MET_LINK_SCAN_DONE:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 12;
            break;
        case SYS_INTR_FUNC_OAM_AUTO_GEN:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 13;
            break;
        case SYS_INTR_FUNC_OAM_DEFECT_CACHE:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 14;
            break;
        case SYS_INTR_FUNC_DP1_MDIO_XG_CHANGE_0:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 15;
            break;
        case SYS_INTR_FUNC_DP1_MDIO_XG_CHANGE_1:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 16;
            break;
        case SYS_INTR_FUNC_MDIO_XG_CHANGE_0:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 17;
            break;
        case SYS_INTR_FUNC_MDIO_XG_CHANGE_1:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 18;
            break;
        case SYS_INTR_FUNC_SPN_DMA_DROPL:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 19;
            break;
        case SYS_INTR_FUNC_SPN_DMA_DROPM:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 20;
            break;
        case SYS_INTR_FUNC_SPN_CPU_REPORTL:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 21;
            break;
        case SYS_INTR_FUNC_SPN_CPU_REPORTM:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 22;
            break;
        case SYS_INTR_FUNC_CPU_MAC:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 23;
            break;
        case SYS_INTR_FUNC_BSR_C2C_PKT_CONGESTION:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 24;
            break;
        case SYS_INTR_FUNC_BSR_CRITICAL_PKT_CONGESTION:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 25;
            break;
        case SYS_INTR_FUNC_BSR_DMA_CONGESTION:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 26;
            break;
        case SYS_INTR_FUNC_BSR_OAM_CONGESTION:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 27;
            break;
        case SYS_INTR_FUNC_BSR_TOTAL_CONGESTION:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 28;
            break;
        case SYS_INTR_FUNC_DP1_BSR_C2C_PKT_CONGESTION:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 29;
            break;
        case SYS_INTR_FUNC_DP1_BSR_CRITICAL_PKT_CONGESTION:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 30;
            break;
        case SYS_INTR_FUNC_DP1_BSR_DMA_CONGESTION:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 31;
            break;
        case SYS_INTR_FUNC_DP1_BSR_OAM_CONGESTION:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 32;
            break;
        case SYS_INTR_FUNC_DP1_BSR_TOTAL_CONGESTION:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 33;
            break;
        case SYS_INTR_FUNC_FLEX_DP0:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 34;
            break;
        case SYS_INTR_FUNC_FLEX_DP1:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 35;
            break;
        case SYS_INTR_FUNC_OMC_TR:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 36;
            break;
        case SYS_INTR_FUNC_OMC_TL:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 37;
            break;
        case SYS_INTR_FUNC_OMC_BR:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 38;
            break;
        case SYS_INTR_FUNC_OMC_BL:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 39;
            break;
        case SYS_INTR_FUNC_DP0_MACSEC_RX:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 40;
            break;
        case SYS_INTR_FUNC_DP1_MACSEC_RX:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 41;
            break;
        case SYS_INTR_FUNC_DP0_MACSEC_TX:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 42;
            break;
        case SYS_INTR_FUNC_DP1_MACSEC_TX:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 43;
            break;
        case SYS_INTR_FUNC_DP0_MC_MAC0:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 44;
            break;
        case SYS_INTR_FUNC_DP0_MC_MAC1:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 45;
            break;
        case SYS_INTR_FUNC_DP0_MC_MAC2:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 46;
            break;
        case SYS_INTR_FUNC_DP0_MC_MAC3:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 47;
            break;
        case SYS_INTR_FUNC_DP1_MC_MAC0:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 48;
            break;
        case SYS_INTR_FUNC_DP1_MC_MAC1:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 49;
            break;
        case SYS_INTR_FUNC_DP1_MC_MAC2:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 50;
            break;
        case SYS_INTR_FUNC_DP1_MC_MAC3:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 51;
            break;
        case SYS_INTR_FUNC_PTP_TOD_PULSE:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 52;
            break;
        case SYS_INTR_FUNC_PTP_SYNC_PULSE:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 53;
            break;
        case SYS_INTR_FUNC_FLEXE0_MCU_REQ:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 54;
            break;
        case SYS_INTR_FUNC_FLEXE1_MCU_REQ:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 55;
            break;
        case SYS_INTR_FUNC_MISC_MCU_REQ:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 56;
            break;
        case SYS_INTR_PCIE_BURST_DONE:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 57;
            break;
        case SYS_INTR_DMA:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 58;
            break;
        case SYS_INTR_FUNC_ECPU:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 59;
            break;
        case SYS_INTR_FUNC_SCPU:
            *p_sup_table_id = SupIntrFunc_t;
            *p_bit_offset = 60;
            break;
        default:
            *p_sup_table_id = 0; /* invalid value, must keep value is 0 */
            *p_bit_offset = 0xFFFF; /* invalid value */
            return CTC_E_NOT_SUPPORT;
            break;
    }


    if (p_func_table_id)
    {
        switch (intr_type)
        {
            case SYS_INTR_FUNC_OAM_AUTO_GEN:
                *p_func_table_id = OamAutoGenPktInterruptFunc_t;
                break;
            case SYS_INTR_FUNC_CPU_MAC:
                *p_func_table_id = CpuMacProcInterruptFunc_t;
                break;
            case SYS_INTR_PCIE_BURST_DONE:
                *p_func_table_id = PcieIntfInterruptFunc_t;
                break;
            case SYS_INTR_DMA:
                *p_func_table_id = DRV_FROM_AT(lchip)? DmaCtlIntrFunc0_t : DmaCtlIntrFunc_t;
                break;
                /*
            case SYS_INTR_FUNC_ECPU:
                *p_func_table_id = IntrIntCtl_t;
                break;
            case SYS_INTR_FUNC_SCPU:
                *p_func_table_id = ScpuIntrIntCtl_t;
                break;
                */
            case SYS_INTR_FUNC_DP0_MC_MAC0:
                *p_func_table_id = CtcHsCtlInterruptFunc_t | (0<<24);
                break;
            case SYS_INTR_FUNC_DP0_MC_MAC1:
                *p_func_table_id = CtcHsCtlInterruptFunc_t | (1<<24);
                break;
            case SYS_INTR_FUNC_DP0_MC_MAC2:
                *p_func_table_id = CtcCsCtlInterruptFunc_t | (0<<24);
                break;
            case SYS_INTR_FUNC_DP0_MC_MAC3:
                *p_func_table_id = CtcCsCtlInterruptFunc_t | (1<<24);
                break;
            case SYS_INTR_FUNC_DP1_MC_MAC0:
                *p_func_table_id = CtcHsCtlInterruptFunc_t | (2<<24);
                break;
            case SYS_INTR_FUNC_DP1_MC_MAC1:
                *p_func_table_id = CtcHsCtlInterruptFunc_t | (3<<24);
                break;
            case SYS_INTR_FUNC_DP1_MC_MAC2:
                *p_func_table_id = CtcCsCtlInterruptFunc_t | (2<<24);
                break;
            case SYS_INTR_FUNC_DP1_MC_MAC3:
                *p_func_table_id = CtcCsCtlInterruptFunc_t | (3<<24);
                break;
            case SYS_INTR_FUNC_FLEX_DP0:
                *p_func_table_id = FlexeMgrInterruptFunc_t | (0<<24);
                break;
            case SYS_INTR_FUNC_FLEX_DP1:
                *p_func_table_id = FlexeMgrInterruptFunc_t | (1<<24);
                break;
            default:
                *p_func_table_id = 0;/* other type return invalid table id, include fatal and normal */
                break;
        }
    }

    return CTC_E_NONE;
}

/*Notice: In this function, sys_intr_type_t is tmm sys_tmm_interrupt_type_t */
int32
sys_tmm_interrupt_get_status_func(uint8 lchip, sys_intr_type_t* p_type, uint32* p_bmp)
{
    uint32 cmd = 0;
    uint32 value[CTC_INTR_STAT_SIZE] = {0};
    uint32 mask[CTC_INTR_STAT_SIZE] = {0};
    uint32 tbl_id = 0;
    uint8 ins_num = 0;
    uint8 tbl_size = 0;
    uint8 index = 0;

    if (p_usw_intr_master[lchip]->p_intr_func[p_type->intr].sub_tbl_id)
    {
        tbl_id = p_usw_intr_master[lchip]->p_intr_func[p_type->intr].sub_tbl_id;
        tbl_size =  p_usw_intr_master[lchip]->p_intr_func[p_type->intr].tbl_size;
    }
    else
    {
        tbl_id = p_usw_intr_master[lchip]->p_intr_func[p_type->intr].tbl_id;
        tbl_size = p_usw_intr_master[lchip]->intr_word_num;
    }

    ins_num = (tbl_id >> 24)&0xFF;
    tbl_id = tbl_id&0xFFFFFF;

    cmd = DRV_IOR((tbl_id), DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, INTR_INDEX_VAL_SET + ins_num * INTR_INDEX_MAX, cmd, value));
    cmd = DRV_IOR((tbl_id), DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, INTR_INDEX_MASK_SET + ins_num * INTR_INDEX_MAX, cmd, mask));

    for(index = 0; index < tbl_size; index++)
    {
        p_bmp[index] = value[index] & (~mask[index]);
    }

    return CTC_E_NONE;
}


/*Notice: In this function, sys_intr_type_t is tsingma sys_tm_interrupt_type_t */
int32
sys_tmm_interrupt_clear_status_func(uint8 lchip, uint32 intr, uint32* bmp)
{
    uint32 cmd = 0;
    uint32 tbl_id = 0;
    uint32 sup_bmp[2] = {0};
    uint8 ins_num = 0;

    if (p_usw_intr_master[lchip]->p_intr_func[intr].sub_tbl_id)
    {
        tbl_id = p_usw_intr_master[lchip]->p_intr_func[intr].sub_tbl_id;
        ins_num = (tbl_id >> 24)&0xFF;
        tbl_id = tbl_id&0xFFFFFF;
        cmd = DRV_IOW((tbl_id), DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, INTR_INDEX_VAL_RESET+ ins_num * INTR_INDEX_MAX, cmd, bmp));
        
#if ((SDK_WORK_PLATFORM == 1) || ((0 == SDK_WORK_PLATFORM) && (1 == SDK_WORK_ENV)))  /* simulation */
        _sys_usw_interrupt_model_sim_value(lchip, tbl_id, p_usw_intr_master[lchip]->p_intr_func[intr].common_type, bmp, FALSE);
#endif
    }


    CTC_BMP_SET(sup_bmp, (intr-2));
    cmd = DRV_IOW(SupIntrFunc_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, INTR_INDEX_VAL_RESET, cmd, sup_bmp));

#if ((SDK_WORK_PLATFORM == 1) || ((0 == SDK_WORK_PLATFORM) && (1 == SDK_WORK_ENV)))  /* simulation */
    _sys_usw_interrupt_model_sim_value(lchip, SupIntrFunc_t, p_usw_intr_master[lchip]->p_intr_func[intr].common_type, sup_bmp, FALSE);
#endif
    return CTC_E_NONE;
}

int32
sys_tmm_interrpt_dispatch_func(uint8 lchip, uint32* p_status)
{
    uint8 intr_idx = 0;
    sys_intr_type_t type;
    sys_intr_t* p_intr = NULL;
    uint32 status[CTC_INTR_STAT_SIZE] = {0};
    sys_intr_func_intr_info_t* p_func_intr_tmm;

    for(intr_idx = SYS_TMM_INTR_FUNC_PTP_TS_CAPTURE_FIFO; intr_idx < SYS_TMM_INTR_MAX; intr_idx++)
    {
        if (!CTC_BMP_ISSET(p_status, intr_idx))
        {
            continue;
        }
        p_func_intr_tmm = &p_usw_intr_master[lchip]->p_intr_func[intr_idx];

        /*get intr status*/
        type.intr = intr_idx;
        type.sub_intr = INVG;
        type.low_intr = INVG;
        type.slice_id = 0;
        sys_tmm_interrupt_get_status_func(lchip, &type, status);

        p_intr = &(p_usw_intr_master[lchip]->intr[p_func_intr_tmm->common_type]);
        if (p_intr->is_event)
        {
            CTC_ERROR_RETURN(sys_tmm_interrupt_clear_status_func(lchip, intr_idx, status));/* status keep original value */
        }

        if (p_intr->valid)
        {
            p_intr->occur_count++;
            if (p_intr->isr)
            {
                SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_INFO,"Dispatch interrupt intr: %d, count: %d\n", p_func_intr_tmm->common_type, p_intr->occur_count);
                p_intr->isr(lchip, p_func_intr_tmm->common_type, status);
            }
        }

        if (!p_intr->is_event)
        {
            CTC_ERROR_RETURN(sys_tmm_interrupt_clear_status_func(lchip, intr_idx, status));
        }
    }

    return CTC_E_NONE;
}

#define SYS_INTR_FLEXE_MGR_INTR_BIT  2
#define SYS_INTR_FLEXE_SHIM_INTR_BIT  3

int32
sys_tmm_interrut_dispatch_flexe(uint8 lchip, uint32 sub_tbl_id)
{
    uint32 cmd = 0;
    uint32 flex_normal;
    sys_intr_t* p_intr = NULL;
    uint32 status[CTC_INTR_STAT_SIZE] = {0};
    uint32 tbl_id = 0;
    uint8 ins_id = 0;
    uint8 index = 0;
    uint32 tbl_id1 = 0;
    uint32 val32   = 0;

    sys_intr_flexe_status_t flexe_status;
    RxIntMaskInst0_m    flexe_mask;

    if ((sub_tbl_id&0xFFFFFF) != CtcFlexeShimInterruptNormal_t)
    {
        SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP,"Flexe Normal dispatch error! tbl id mismatch, sub_tbl_id: 0x%x\n", sub_tbl_id);
        return CTC_E_NONE;
    }

    sal_memset(&flexe_status, 0, sizeof(flexe_status));
    p_intr = &(p_usw_intr_master[lchip]->intr[SYS_INTR_FUNC_FLEX_DP0]);
    if (!p_intr->valid || !p_intr->isr)
    {
        return CTC_E_NONE;
    }

    ins_id = (sub_tbl_id >> 24)&0xFF;
    cmd = DRV_IOR(sub_tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(ins_id, INTR_INDEX_VAL_SET), cmd, &flex_normal));
    if (CTC_IS_BIT_SET(flex_normal, SYS_INTR_FLEXE_MGR_INTR_BIT))
    {
        tbl_id = FlexeMgrInterruptNormal_t;
        cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(ins_id,INTR_INDEX_VAL_SET), cmd, status));
        if (status[0] || status[1])
        {
            /*dispatch to flexe function*/
            flexe_status.p_status = status;
            flexe_status.dir = 0;
            flexe_status.dp  = ins_id;
            
            p_intr->isr(lchip, SYS_INTR_CHIP_NORMAL, &flexe_status);

            cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(ins_id,INTR_INDEX_VAL_RESET), cmd, status));
        }
    }

    if (CTC_IS_BIT_SET(flex_normal, SYS_INTR_FLEXE_SHIM_INTR_BIT))
    {
        /*process rx*/
        for (index = 0; index < 8; index++)
        {
            tbl_id = RxLatchedIntInst0_t;
            tbl_id += (RxLatchedIntInst1_t - RxLatchedIntInst0_t)*index;
            cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(ins_id,0), cmd, status));

            if (0x840c == (status[0] & 0x840c)) /* calSwitchEv/ohlock/ohmflock/deskew must be 1 */
            {
                flexe_status.evt_bmp = 0;
                
                /* mask */
                tbl_id1 = RxIntMaskInst0_t;
                tbl_id1 += (RxIntMaskInst1_t - RxIntMaskInst0_t)*index;
                cmd = DRV_IOR(tbl_id1, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(ins_id,0), cmd, &flexe_mask));
                val32 = 0;
                SetRxIntMaskInst0(V, calSwitchEv_f, &flexe_mask, val32);
                
                cmd = DRV_IOW(tbl_id1, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(ins_id,0), cmd, &flexe_mask));
            }

            if (0x840c == (status[0] & 0x840c)) /* calSwitchEv/ohlock/ohmflock/deskew must be 1 */
            {
                flexe_status.p_status = status;
                flexe_status.flexe_ins = index;
                flexe_status.dir = 0;  /* RX */
                flexe_status.dp  = ins_id;
                flexe_status.evt_bmp |= (1 << CTC_FLEXE_EVENT_RX_SWITCH_OK);
                p_intr->isr(lchip, SYS_INTR_CHIP_NORMAL, &flexe_status);
            }

            /* clear */
            tbl_id = RxGblClrInst0_t;
            tbl_id += (RxGblClrInst1_t - RxGblClrInst0_t)*index;
            cmd = DRV_IOW(tbl_id, RxGblClrInst0_intClearSC_f);
            val32 = 1;
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, DRV_INS(ins_id,0), cmd, &val32));

            if (0x840c == (status[0] & 0x840c)) /* calSwitchEv/ohlock/ohmflock/deskew must be 1 */
            {
                /* unmask */
                tbl_id1 = RxIntMaskInst0_t;
                tbl_id1 += (RxIntMaskInst1_t - RxIntMaskInst0_t)*index;
                cmd = DRV_IOR(tbl_id1, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(ins_id,0), cmd, &flexe_mask));
                val32 = 1;
                SetRxIntMaskInst0(V, calSwitchEv_f, &flexe_mask, val32);
              
                cmd = DRV_IOW(tbl_id1, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(ins_id,0), cmd, &flexe_mask));
            }
        }
    }

    if (flex_normal & 0x3)
    {
        ctc_interrupt_abnormal_status_t abnormal_status;
        uint8 gchip = 0;

        if (p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR])
        {
            sal_memset(&abnormal_status, 0, sizeof(ctc_interrupt_abnormal_status_t));
            sys_usw_get_gchip_id(lchip, &gchip);
            abnormal_status.type.intr = CTC_INTR_CHIP_NORMAL;
            abnormal_status.type.sub_intr = 20+ins_id;
            abnormal_status.action = CTC_INTERRUPT_FATAL_INTR_LOG;

            if (flex_normal & 0x1)
            {
                abnormal_status.type.low_intr = 0;
                p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR](gchip, &abnormal_status);
            }

            if (flex_normal & 0x2)
            {
                abnormal_status.type.low_intr = 1;
                p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR](gchip, &abnormal_status);
            }
        }
    }

    /*clear sub interrupt*/
    cmd = DRV_IOW(sub_tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, DRV_INS(ins_id,INTR_INDEX_VAL_RESET), cmd, &flex_normal));

    return CTC_E_NONE;
}

static INLINE int32
sys_tmm_interrupt_normal_process(uint8 lchip, sys_intr_type_t* p_type, uint32 intr_bit, ctc_interrupt_abnormal_status_t* p_abnormal_status)
{    
    tbls_id_t intr_tbl = MaxTblId_t;
    int32 ret = 0;
    uint8 action_type = 0;
    uint8 ecc_or_parity = 0;  
    uint8 gchip = 0 ;
    
    sys_usw_interrupt_get_info(lchip, p_type, intr_bit, &intr_tbl, &action_type, &ecc_or_parity);
    
    if (ecc_or_parity)
    {
        /* function interrupt for process ecc or parity */
        sys_usw_interrupt_proc_ecc_or_parity(lchip, intr_tbl, intr_bit, p_abnormal_status->type);
    }
    else if (p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR])
    {
        SYS_USW_INTR_ABNORMAL_LOG_PROCESS(lchip, CTC_INTR_CHIP_NORMAL, p_abnormal_status->type.sub_intr, 
        p_abnormal_status->type.low_intr, p_abnormal_status->status.bmp);
        ret = sys_usw_get_gchip_id(lchip, &gchip);
        if (0 == ret)
        {
            p_usw_intr_master[lchip]->event_cb[CTC_EVENT_ABNORMAL_INTR](gchip, p_abnormal_status);
        }
    }   
    
    return CTC_E_NONE;
}

int32
sys_tmm_interrut_isr_sup_normal(uint8 lchip, uint32 intr, void* p_data)
{
    uint32* p_sup_normal = (uint32*)p_data;
    sys_intr_type_t type;
    uint32 idx = 0;
    uint32 offset = 0;
    uint32 i = 0;
    uint32 j = 0;
    ctc_interrupt_abnormal_status_t abnormal_status;
    ctc_intr_status_t* p_status = &(abnormal_status.status);
    int32 ret = CTC_E_NONE;
    uint32  sub_bmp[CTC_INTR_STAT_SIZE] = {0};
    uint32  low_bmp[CTC_INTR_STAT_SIZE] = {0};
    uint32 cpumac_fcdl = 0;
    uint16 mac_id = 0;
    uint8 loop = 0;
    uint8 level4_valid = 0;    
    sal_memset(&abnormal_status, 0, sizeof(abnormal_status));
    sal_memset(&type, 0, sizeof(sys_intr_type_t));

    type.intr = SYS_INTR_CHIP_NORMAL;

    /* 2. get & clear sub interrupt status */
    for (i = 0; i < p_usw_intr_master[lchip]->normal_sub_cnt; i++)
    {
        level4_valid = 0;
        
        idx = i / CTC_UINT32_BITS;
        offset = i % CTC_UINT32_BITS;

        if (0 == p_sup_normal[idx])
        {
            /* bypass 32Bit 0 */
            i = (idx + 1) * CTC_UINT32_BITS-1;
            continue;
        }

        if (!CTC_IS_BIT_SET(p_sup_normal[idx], offset))
        {
            continue;
        }
        type.sub_intr = i;
        type.low_intr = INVG;
        type.lvl4_intr = INVG;

        /* get sub interrupt status */
        _sys_usw_interrupt_get_status_normal(lchip, &type, sub_bmp);

        if (!sub_bmp[0] && !sub_bmp[1] && !sub_bmp[2])
        {
            continue;
        }

        for (j = 0; j < CTC_INTR_STAT_SIZE * CTC_UINT32_BITS; j++)
        {
            if(!CTC_BMP_ISSET(sub_bmp, j))
            {
                continue;
            }

            if (i == 20 || i == 21)
            {
                uint32 sub_tbl_id = 0;
                sub_tbl_id = CtcFlexeShimInterruptNormal_t|((i == 21?1:0)<<24);
                MCHIP_INTR(lchip)->interrupt_dispatch_flexe(lchip, sub_tbl_id);
                continue;
            }

            sal_memset(low_bmp, 0, sizeof(low_bmp));
            type.low_intr = j;
            abnormal_status.type.intr = CTC_INTR_CHIP_NORMAL;
            abnormal_status.type.sub_intr = i;
            abnormal_status.type.low_intr = j;

            /* get low interrupt status */
            ret = _sys_usw_interrupt_get_status_normal(lchip, &type, low_bmp);
            if (ret < 0)
            {
                continue;
            }
            SYS_INTR_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "sup-intr:%d sub-intr:%d low-intr:%d\n",type.intr,type.sub_intr,type.low_intr);

            for(loop = 0; loop < CTC_INTR_STAT_SIZE; loop++)
            {
                if(low_bmp[loop])
                {
                    level4_valid = 1;
                    break;
                }
            }
            
            if(!level4_valid)
            {
                /* no low table id */
                abnormal_status.type.intr = CTC_INTR_CHIP_NORMAL;
                abnormal_status.type.sub_intr = i;
                abnormal_status.type.low_intr = j;
                abnormal_status.action = CTC_INTERRUPT_FATAL_INTR_LOG;

                sys_tmm_interrupt_normal_process(lchip, &type, j, &abnormal_status);  
                continue;
            }

            /*have low level interrupt*/
            cpumac_fcdl = 0;
            if (type.sub_intr == 19 && type.low_intr == 4)
            {
                uint32 cmd = 0;
                uint32 value[2] = {0};
                uint32 mask[2] = {0};
                /*TMM cpumac fcdl have 4nd level, need adjust before low level dispatch*/
                cmd = DRV_IOR(QuadSgmacInterruptNormal_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, INTR_INDEX_VAL_SET, cmd, value));

                cmd = DRV_IOR(QuadSgmacInterruptNormal_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, mask));

                value[0] = (value[0] & (~mask[0]));
                value[1] = (value[1] & (~mask[1]));
                cpumac_fcdl = value[0]&0x3C0000;
            }

            /*Process fcdl*/
            if ((type.sub_intr <= 7 && (type.low_intr == 70 || type.low_intr == 33) &&
               (low_bmp[7]&0xFFFF0000 || low_bmp[8]&0xFFFFFF)) || cpumac_fcdl)
            {
                uint32 cmd = 0;
                /*normal mac fcdl*/
                for (loop = 0; loop < 40; loop ++)
                {
                    if (CTC_BMP_ISSET(low_bmp, (240 + loop)))
                    {
                        mac_id = (7 - type.sub_intr) * 40 + loop;
                        sys_usw_qos_fcdl_state_isr(lchip, mac_id);
                    }
                }

                /*cpumac fcdl*/
                for (loop = 0; loop < 4; loop ++)
                {
                    if(CTC_IS_BIT_SET(cpumac_fcdl, (18 + loop)))
                    {
                        mac_id = SYS_CPU_MAC_ID_MIN + loop;
                        sys_usw_qos_fcdl_state_isr(lchip, mac_id);
                    }
                }     

                if (cpumac_fcdl)
                {
                    cmd = DRV_IOW(QuadSgmacInterruptNormal_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, INTR_INDEX_VAL_RESET, cmd, &cpumac_fcdl));
                }
                
                /* clear low interrupt status in one time */
                CTC_ERROR_RETURN(_sys_usw_interrupt_clear_status_normal(lchip, &type, low_bmp));
            }
            else
            {
                uint16 k = 0;

                /* process all low interrupt*/
                for (k = 0; k < CTC_INTR_STAT_SIZE * CTC_UINT32_BITS; k++)
                {
                    if (!CTC_BMP_ISSET(low_bmp, k))
                    {
                        continue;
                    }

                    /* no end table id */
                    abnormal_status.type.intr = CTC_INTR_CHIP_NORMAL;
                    abnormal_status.type.sub_intr = i;
                    abnormal_status.type.low_intr = j;
                    abnormal_status.action = CTC_INTERRUPT_FATAL_INTR_LOG;
                    sal_memcpy(p_status->bmp, low_bmp, sizeof(uint32)*CTC_INTR_STAT_SIZE);
                    sys_tmm_interrupt_normal_process(lchip, &type, k, &abnormal_status);                
                }

                /* clear low interrupt status in one time */
                CTC_ERROR_RETURN(_sys_usw_interrupt_clear_status_normal(lchip, &type, low_bmp));
            }
        }
        /*clear sub interrup status*/
        type.low_intr = INVG;
        CTC_ERROR_RETURN(_sys_usw_interrupt_clear_status_normal(lchip, &type, sub_bmp));
    }

    return CTC_E_NONE;
}

int32
sys_tmm_interrupt_init_reg(uint8 lchip)
{
    sys_intr_group_t* p_group = NULL;
    ds_t map_ctl;
    SupIntrGenCtl_m gen_ctl;
    uint32 cmd = 0;
    uint32 i = 0;
    uint32 j = 0;
    uint32 mask_set = 0;
    uint32 unmask_set = 0;
    uint32 value_set = 0;
    uint8 step = 0;
    sys_intr_type_t type;
    uint32 value[CTC_INTR_STAT_SIZE] = {0};
    PcieIntfInterruptNormal_m pcie_normal;
    NetTxInterruptNormal_m    nettx_normal;
    QuadSgmacInterruptNormal0_m quadsgmac_normal;
    IpeAclInterruptNormal_m ipe_acl_normal;
    ds_t ds;
    uint32 intr_bmp[SYS_INTR_MAX_BMP_NUM] = {0};
    uint8 index = 0;
    
    sal_memset(map_ctl, 0, sizeof(map_ctl));
    sal_memset(&quadsgmac_normal, 0, sizeof(QuadSgmacInterruptNormal0_m));
    sal_memset(&gen_ctl, 0, sizeof(gen_ctl));

    mask_set = 0xFF;

    for (i = 0; i < SYS_USW_MAX_INTR_GROUP; i++)
    {
        p_group = &(p_usw_intr_master[lchip]->group[i]);
        if (p_group->group < 0)
        {
            continue;
        }

        if (p_group->group >= 0)
        {
            CTC_BIT_UNSET(mask_set, p_group->irq_idx);
        }

        switch (p_group->irq_idx)
        {
            case 0:
                GetSupIntrMapCtl(A, supIntrMap0_f, &map_ctl, intr_bmp);
                for (index = 0; index < SYS_INTR_MAX_BMP_NUM; index++)
                {
                    intr_bmp[index] |= p_group->intr_bmp[index];
                }
                SetSupIntrMapCtl(A, supIntrMap0_f, &map_ctl, intr_bmp);
                break;

            case 1:
                GetSupIntrMapCtl(A, supIntrMap1_f, &map_ctl, intr_bmp);
                for (index = 0; index < SYS_INTR_MAX_BMP_NUM; index++)
                {
                    intr_bmp[index] |= p_group->intr_bmp[index];
                }
                SetSupIntrMapCtl(A, supIntrMap1_f, &map_ctl, intr_bmp);
                break;

            case 2:
                GetSupIntrMapCtl(A, supIntrMap2_f, &map_ctl, intr_bmp);
                for (index = 0; index < SYS_INTR_MAX_BMP_NUM; index++)
                {
                    intr_bmp[index] |= p_group->intr_bmp[index];
                }
                SetSupIntrMapCtl(A, supIntrMap2_f, &map_ctl, intr_bmp);
                break;

            case 3:
                GetSupIntrMapCtl(A, supIntrMap3_f, &map_ctl, intr_bmp);
                for (index = 0; index < SYS_INTR_MAX_BMP_NUM; index++)
                {
                    intr_bmp[index] |= p_group->intr_bmp[index];
                }
                SetSupIntrMapCtl(A, supIntrMap3_f, &map_ctl, intr_bmp);
                break;

            default:
                break;
        }
    }

    unmask_set = (~mask_set)&0xff;

    SetSupIntrGenCtl(V, supIntrMaskSet_f, &gen_ctl, mask_set);
    SetSupIntrGenCtl(V, supIntrMaskClr_f, &gen_ctl, unmask_set);
    cmd = DRV_IOW(SupIntrMapCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &map_ctl));
    cmd = DRV_IOW(SupIntrGenCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &gen_ctl));

    /* release fatal interrupt mask */
    for (i = 0; i < p_usw_intr_master[lchip]->fatal_sub_cnt; i++)
    {
        /* force release sub intr even if no lower interrupt*/
        j = 0;
        do
        {
            type.intr = SYS_INTR_CHIP_FATAL;
            type.sub_intr = i;
            type.low_intr = j;
            _sys_usw_interrupt_release_fatal(lchip, &type, 1);
            j++;
        }
        while (j < p_usw_intr_master[lchip]->p_intr_low_fatal[i].array_size);
    }

    /* release normal interrupt mask */
    for (i = 0; i < p_usw_intr_master[lchip]->normal_sub_cnt; i++)
    {
        /* force release sub intr even if no lower interrupt*/
        j = 0;
        do
        {
            type.intr = SYS_INTR_CHIP_NORMAL;
            type.sub_intr = i;
            type.low_intr = j;
            _sys_usw_interrupt_release_normal(lchip, &type, 1);
            j++;
        }
        while (j < p_usw_intr_master[lchip]->p_intr_low_normal[i].array_size);
    }

    cmd = DRV_IOR(PbCtlLeftInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(PbCtlLeftInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(PbCtlLeftInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET + INTR_INDEX_MAX, cmd, value);
    cmd = DRV_IOW(PbCtlLeftInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET + INTR_INDEX_MAX, cmd, value);

    cmd = DRV_IOR(CpuMapInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(CpuMapInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(PcieIntfInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(PcieIntfInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(DmaCtlInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(DmaCtlInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(PbCtlLeftInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(PbCtlLeftInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(PbCtlLeftInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET + INTR_INDEX_MAX, cmd, value);
    cmd = DRV_IOW(PbCtlLeftInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET + INTR_INDEX_MAX, cmd, value);

    cmd = DRV_IOR(I2CMasterInterruptNormal0_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(I2CMasterInterruptNormal0_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(I2CMasterInterruptNormal1_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(I2CMasterInterruptNormal1_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(CpuMapInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(CpuMapInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(PcieIntfInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(PcieIntfInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    cmd = DRV_IOR(DmaCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    cmd = DRV_IOW(DmaCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    value[0] = 0x807C3006;
    value[1] = 0x0000000F;

    cmd = DRV_IOW(DmaCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);

    cmd = DRV_IOR(SupIntrFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value_set);
    cmd = DRV_IOW(SupIntrFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value_set);

    /* release function interrupt mask*/
    cmd = DRV_IOR(DmaCtlIntrFunc_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value_set);
    cmd = DRV_IOW(DmaCtlIntrFunc_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value_set);

    /* release function cpumac mask*/
    if (!DRV_IS_TMG(lchip))
    {
        cmd = DRV_IOR(CpuMacProcInterruptFunc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);
        cmd = DRV_IOW(CpuMacProcInterruptFunc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &ds);
    }

    cmd = DRV_IOR(CpuMacProcInterruptFunc1_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);
    cmd = DRV_IOW(CpuMacProcInterruptFunc1_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &ds);

    for(i = 0; i < 4; i++)
    {
        sal_memset(value, 0, sizeof(value));
        SetCtcHsCtlInterruptFunc(V, funcIntrHataTxTsToCpuFifo_f, value, 1);
        cmd = DRV_IOW(CtcHsCtlInterruptFunc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET + (i * INTR_INDEX_MAX), cmd, &value);

        sal_memset(value, 0, sizeof(value));
        SetCtcCsCtlInterruptFunc(V, funcIntrHataTxTsToCpuFifo_f, value, 1);
        cmd = DRV_IOW(CtcCsCtlInterruptFunc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET + (i * INTR_INDEX_MAX), cmd, &value);

        sal_memset(&ds, 0, sizeof(ds_t));
        /*intrSgmiiAnRemoteAnegErr/intrSgmiiAnRemoteLinkFailure/intrSgmiiAnRemoteOffline*/
        ds[3] = 0x3FFFFF;
        /*intrFlexeTxBufUnderrun0*/
        ds[2] = 0xC0003FFF;
        /*intrRxFecDegradedPam4Chan/intrRxLocalDegradedBsChan/intrRxRemoteDegradedBsChan/intrRxAsyncFifoOverrunLane0*/
        ds[1] = 0xFFFCFF00;
        /*intrTxFifoUnderrunLane/intrTxBufOverrunLane*/
        ds[0] = 0x0000FFFF;
        cmd = DRV_IOW(McPcsX8LanesInterruptNormal_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, DRV_INS(i, INTR_INDEX_MASK_SET), cmd, &ds);

        sal_memset(&ds, 0, sizeof(ds_t));
        /*intrSgmiiAnRemoteAnegErr*/
        ds[5] = 0x00003FFF;
        /*intrSgmiiAnRemoteAnegErr/intrSgmiiAnRemoteLinkFailure/intrSgmiiAnRemoteOffline*/
        ds[4] = 0xFFFFFFFF;
        /*intrSgmiiAnRemoteOffline/intrTxBufOverrunLane*/
        ds[3] = 0xC0003FFF;
        /*intrRxFecDegradedPam4Chan/intrRxLocalDegradedBsChan/intrRxRemoteDegradedBsChan/intrRxAsyncFifoOverrunLane*/
        ds[2] = 0xFFFE7FFF;
        /**/
        ds[1] = 0x0;
        /*intrTxFifoUnderrunLane*/
        ds[0] = 0x0000FFFF;
        cmd = DRV_IOW(McPcsX16LanesInterruptNormal_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, DRV_INS(i, INTR_INDEX_MASK_SET), cmd, &ds);

        sal_memset(&ds, 0, sizeof(ds_t));
        /*intrHssPhyReadyChg/intrHssPllLockChg/intrHssSigDetectChg*/
        ds[0] = 0x00FFFFFF;
        cmd = DRV_IOW(CtcCsCtlInterruptNormal_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, DRV_INS(i, INTR_INDEX_MASK_SET), cmd, &ds);

        sal_memset(&ds, 0, sizeof(ds_t));
        /*intrHssPhyReadyChg*/
        ds[1] = 0x0000FFFF;
        /*intrHssPllLockChg/intrHssSigDetectChg*/
        ds[0] = 0xFFFFFFFF;
        cmd = DRV_IOW(CtcHsCtlInterruptNormal_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, DRV_INS(i, INTR_INDEX_MASK_SET), cmd, &ds);
    }

    
    sal_memset(&ds, 0, sizeof(ds_t));
    /*anRemoteAnegErr/anRemoteLinkFailure/anRemoteOffline*/
    ds[0] = 0x0000FFF0;
    cmd = DRV_IOW(SharedPcsInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);

    sal_memset(&ds, 0, sizeof(ds_t));
    /* FlexeMgrInterruptFunc */
    ds[0] = 0;
    ds[1] = 0xF7FFBFFD;
    ds[2] = 0xFFDFFEFF;
    ds[3] = 0xEFFF7FFB;
    ds[4] = 0xFFFFFFFF;
    cmd = DRV_IOW(FlexeMgrInterruptFunc_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, DRV_INS(0, INTR_INDEX_MASK_RESET), cmd, &ds);
    DRV_IOCTL(lchip, DRV_INS(1, INTR_INDEX_MASK_RESET), cmd, &ds);

    sal_memset(&ds, 0, sizeof(ds_t));
    /*intRxLintFault/intRxRemoteFault/intRxLocalFault/intRxLinkFault*/
    ds[0] = 0x0000FFFF;
    cmd = DRV_IOW(SharedMiiInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);
    sal_memset(&ds, 0, sizeof(ds_t));
    ds[3] = 0xFFFFFFFF;
    ds[2] = 0xFFFFFFFF;
    ds[1] = 0xFFFFFFFF;
    ds[0] = 0xFFFFFFFF;
    cmd = DRV_IOW(EcpuInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);

    sal_memset(&ds, 0, sizeof(ds_t));
    ds[1] = 0xFFFFFFFF;
    ds[0] = 0xFFFFFFFF;
    cmd = DRV_IOW(ScpuInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);

    sal_memset(&ds, 0, sizeof(ds_t));
    /*statsRamOverflow*/
    ds[1] = 0x4000000;
    ds[0] = 0x0;
    cmd = DRV_IOW(GlobalStatsInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);

    sal_memset(&ds, 0, sizeof(ds_t));
    /*encapFifo0Overrun*/
    ds[0] = 0x78000;
    cmd = DRV_IOW(CpuMapInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ds);

    sal_memset(&ds, 0, sizeof(ds_t));
    /*flexeCrossTxInterruptNormal*/
    ds[0] = 0x0004;
    cmd = DRV_IOW(CtcFlexeCrossInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, DRV_INS(0, INTR_INDEX_MASK_SET), cmd, &ds);
    DRV_IOCTL(lchip, DRV_INS(1, INTR_INDEX_MASK_SET), cmd, &ds);

    cmd = DRV_IOR(PcieIntfInterruptFunc_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value_set);
    cmd = DRV_IOW(PcieIntfInterruptFunc_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value_set);

    sal_memset(&nettx_normal, 0, sizeof(NetTxInterruptNormal_m));
    SetNetTxInterruptNormal(V, rxNoEopErrorIntr0_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoEopErrorIntr1_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoEopErrorIntr2_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoEopErrorIntr3_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoSopErrorIntr0_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoSopErrorIntr1_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoSopErrorIntr2_f, &nettx_normal, 1);
    SetNetTxInterruptNormal(V, rxNoSopErrorIntr3_f, &nettx_normal, 1);
    cmd = DRV_IOW(NetTxInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &nettx_normal);

    cmd = DRV_IOR(PcieIntfInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &pcie_normal);
    SetPcieIntfInterruptNormal(V, hssRxAEyeQualityIntr_f, &pcie_normal, 1);
    SetPcieIntfInterruptNormal(V, hssRxBEyeQualityIntr_f, &pcie_normal, 1);
    cmd = DRV_IOW(PcieIntfInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &pcie_normal);

    /*mask IpeAclInterruptNormal.timestampOverrun*/
     cmd = DRV_IOR(IpeAclInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ipe_acl_normal);
    SetIpeAclInterruptNormal(V, timestampOverrun_f, &ipe_acl_normal, 1);
    cmd = DRV_IOW(IpeAclInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &ipe_acl_normal);

    cmd = DRV_IOR(LinkAggInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);
    SetLinkAggInterruptNormal(V, refChanAvgLoadOverlap_f, &value, 1);
    SetLinkAggInterruptNormal(V, refChanAvgQSizeOverlap_f, &value, 1);
    SetLinkAggInterruptNormal(V, refFlowSetActiveUpdateOverlap_f, &value, 1);
    cmd = DRV_IOW(LinkAggInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);

    cmd = DRV_IOR(SvcPolicingInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);
    SetSvcPolicingInterruptNormal(V, scanOverlapIntr_f, &value, 1);
    cmd = DRV_IOW(SvcPolicingInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);

    cmd = DRV_IOR(CtcMiscCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);
    SetCtcMiscCtlInterruptNormal(V, hMacEngineInterruptNormal_f, &value, 1);
    cmd = DRV_IOW(CtcMiscCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);

    /* fix bug118082  Abnormal Interrupt when two ports flow to one port */
    cmd = DRV_IOR(BufStoreProcInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);
    SetBufStoreProcInterruptNormal(V, c2cCntOvf_f, &value, 1);
    SetBufStoreProcInterruptNormal(V, criticalCntOvf_f, &value, 1);
    SetBufStoreProcInterruptNormal(V, g_0_scCntOvf_f, &value, 1);
    SetBufStoreProcInterruptNormal(V, g_1_scCntOvf_f, &value, 1);
    SetBufStoreProcInterruptNormal(V, g_2_scCntOvf_f, &value, 1);
    SetBufStoreProcInterruptNormal(V, g_3_scCntOvf_f, &value, 1);
    SetBufStoreProcInterruptNormal(V, totalCntOvf_f, &value, 1);
    cmd = DRV_IOW(BufStoreProcInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, &value);

    sal_memset(value, 0, sizeof(value));
    SetQuadSgmacInterruptNormal(V, intSgmac0RxPauseLockDetect_f, &value, 1);
    SetQuadSgmacInterruptNormal(V, intSgmac1RxPauseLockDetect_f, &value, 1);
    SetQuadSgmacInterruptNormal(V, intSgmac2RxPauseLockDetect_f, &value, 1);
    SetQuadSgmacInterruptNormal(V, intSgmac3RxPauseLockDetect_f, &value, 1);
    cmd = DRV_IOW(QuadSgmacInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value);

    sal_memset(value, 0, sizeof(value));
    SetCpuMacProcInterruptNormal(V, quadSgmacInterruptNormal_f, &value, 1);
    cmd = DRV_IOW(CpuMacProcInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value);

    sal_memset(value, 0, sizeof(value));
    SetCtcMiscCtlInterruptNormal(V, cpuMacProcInterruptNormal_f, &value, 1);
    cmd = DRV_IOW(CtcMiscCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value);

    sal_memset(value, 0, sizeof(value));
    SetSupIntrNormal(V, rlmMiscNormalIntr_f, &value, 1);
    cmd = DRV_IOW(SupIntrNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &value);

    cmd = DRV_IOR(SupIntrFunc_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, cmd, value);
    value[0] = value[0] & (~(1<<6));/* Tcam Scan Error*/
    cmd = DRV_IOW(SupIntrFunc_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, value);

    /* clear mask pfc normal interrupt*/
    step = QuadSgmacInterruptNormal0_intSgmac1RxPauseLockDetect_f - QuadSgmacInterruptNormal0_intSgmac0RxPauseLockDetect_f;
    for(i = 0; i <= 15; i++)
    {
        for(j = 0; j <= 3; j++)
        {
            SetQuadSgmacInterruptNormal0(V, intSgmac0RxPauseLockDetect_f+j*step, &quadsgmac_normal, 1);
        }
        cmd = DRV_IOW(QuadSgmacInterruptNormal0_t + i, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, cmd, &quadsgmac_normal);
    }

    /*clear some interrupt */
    cmd = DRV_IOR(PcieIntfInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, 0, cmd, &value_set);
    cmd = DRV_IOW(PcieIntfInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, 1, cmd, &value_set);

    cmd = DRV_IOR(PcieIntfInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, 0, cmd, &value_set);
    cmd = DRV_IOW(PcieIntfInterruptFatal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, 1, cmd, &value_set);

    cmd = DRV_IOR(LinkAggInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_VAL_SET, cmd, &value);
    cmd = DRV_IOW(LinkAggInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_VAL_RESET, cmd, &value);

    cmd = DRV_IOR(CtcIpeTxCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_VAL_SET, cmd, &value);
    cmd = DRV_IOW(CtcIpeTxCtlInterruptNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_VAL_RESET, cmd, &value);

    cmd = DRV_IOR(SupIntrNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_VAL_SET, cmd, &value);
    cmd = DRV_IOW(SupIntrNormal_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, INTR_INDEX_VAL_RESET, cmd, &value);

    return CTC_E_NONE;
}


int32
sys_tmm_interrupt_set_sup_op(uint8 lchip, uint8 grp_id, uint8 act_idx)
{
    uint32 cmd = 0;
    SupIntrGenCtl_m sup_ctl;
    uint32 value = 0;

    value = (1 << grp_id);

    sal_memset(&sup_ctl, 0, sizeof(sup_ctl));
    if (INTR_INDEX_VAL_SET == act_idx)
    {
        SetSupIntrGenCtl(V, supIntrValueSet_f, &sup_ctl, value);
    }
    else if (INTR_INDEX_VAL_RESET == act_idx)
    {
        SetSupIntrGenCtl(V, supIntrValueClr_f, &sup_ctl, value);
    }
    else if (INTR_INDEX_MASK_SET == act_idx)
    {
        SetSupIntrGenCtl(V, supIntrMaskSet_f, &sup_ctl, value);
    }
    else
    {
        SetSupIntrGenCtl(V, supIntrMaskClr_f, &sup_ctl, value);

        /*When release msi interrup, clear Pcie0IntrLogCtl_pcie0IntrLogVec_f*/
        if (p_usw_intr_master[lchip]->intr_mode == CTC_INTR_MODE_MSI || p_usw_intr_master[lchip]->intr_mode == CTC_INTR_MODE_MSIX)
        {
            /*TM/TMM process*/
            cmd = DRV_IOR(PcieIntrLogCtl_t, PcieIntrLogCtl_pcieIntrLogVec_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
            CTC_BIT_UNSET(value, grp_id);
            cmd = DRV_IOW(PcieIntrLogCtl_t, PcieIntrLogCtl_pcieIntrLogVec_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        }
    }

    cmd = DRV_IOW(SupIntrGenCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &sup_ctl));
    return CTC_E_NONE;
}

#endif
